Contact & Basic Information
Phone: 6033158359
Email: [email protected]
Join Date:
Department: Electronics And Communication Engineering
Address:
Educations
| Course | Institute | Board / University | Year | Subject |
|---|---|---|---|---|
| M.E. / M.Tech. | National Institute of Technology Silchar | 2017 | Microelectronics & VLSI Design | |
| Ph.D. | National Institute of Technology Silchar | 2022 | Nanoelectronics |
Experiences
| Position | Year | Organisation | Specialisation |
|---|---|---|---|
| Faculty | 09/05/2023 - 07/07/2023 | National Institute of Electronics and Information Technology Aizawl | Teaching |
| Institute Post-Doctoral Fellow | 04/05/2022 04/05/2023 | Indian Institute of Science Education and Research Bhopal | Electrical Engineering and Computer Science Department |
| Assistant Professor Level 10 | 09/05/2023 - 07/07/2023 | Indian Institute of Information Technology Nagpur | Teaching and Research |
Research Interest
Semiconductor Devices, Advanced MOS Devices, Simulation and Modeling, Sensor ApplicationsPublications
| International/National Journals | |||
|---|---|---|---|
| S.No. | Month | Year | Publication Information |
| 1 | JUN | 2025 | S. Kumari, B. S. Saranya, S. M. Joseph and K. Vanlalawmpuia, “Optimization of pocket doped SOI TFET and analysis of interfacial trap charges,” Micro and Nanostructures, vol. 202, June 2025. DOI: https://doi.org/10.1016/j.micrna.2025.208134 |
| 2 | MAR | 2025 | Puja Ghosh, S. Pratap and K. Vanlalawmpuia, “Design and Performance Analysis of TFET with Extended-Dual-Source Structure-Based Label-Free Biosensor,” Journal of Electronic Materials, vol. 54, pp. 4114–4122, March 2025. DOI: https://doi.org/10.1007/s11664-025-11816-8 |
| 3 | FEB | 2025 | K. Vanlalawmpuia and Brinda Bhowmick, “Comparison of Hetero-Stacked Tunnel FET and Delta-Doped Germanium Source Vertical TFET and their Applications,” IETE Journal of Research, pp. 1–15, February 2025. DOI: https://doi.org/10.1080/03772063.2025.2462782 |
| 4 | JAN | 2025 | K. Vanlalawmpuia and Aditya Sankar Medury, “Temperature dependence of analog/RF performance, linearity and harmonic distortion figures of merit in negative capacitance quad-FinFET,” Analog Integrated Circuits and Signal Processing, vol. 122, no. 1, pp. 1–11, January 2025. DOI: https://doi.org/10.1007/s10470-025-02324-0 |
| 5 | AUG | 2024 | Puja Ghosh and K. Vanlalawmpuia, “Design Implementation and RF Analysis of Vertical L-Pattern Gate TFET on SELBOX Substrate,” Transactions on Electrical and Electronic Materials, vol. 25, no. 4, pp. 442–448, August 2024. DOI: https://doi.org/10.1007/s42341-024-00523-6 |
| 6 | MAY | 2024 | K. Vanlalawmpuia, “Investigation of negative differential resistance on negative capacitance Germanium source vertical TFET,” Physica Scripta, vol. 99, no. 6 May 2024. DOI: 10.1088/1402-4896/ad4927 |
| 7 | FEB | 2024 | K. Vanlalawmpuia, Puja Ghosh and Brinda Bhowmick, “Insights into the impact of random dopant fluctuation on ferroelectric germanium source vertical TFET,” Materials Science and Engineering: B, vol. 299, no. 116994, 2024. doi: https://doi.org/10.1016/j.mseb.2023.116994 |
| 8 | DEC | 2023 | K. Vanlalawmpuia and Puja Ghosh, “Performance assessment of dielectrically modulated negative capacitance germanium source vertical tunnel FET biosensor for detection of breast cancer cell lines,” AEU – International Journal of Electronics and Communications, vol. 171, no. 154902, 2023. doi: https://doi.org/10.1016/j.aeue.2023.154902 |
| 9 | NOV | 2023 | K. Vanlalawmpuia and Aditya Sankar Medury, “Engineering negative differential resistance in negative capacitance Quad-FinFET,” Materials Science and Engineering: B, vol. 297, no. 116725, November 2023. doi: https://doi.org/10.1016/j.mseb.2023.116725 |
| 10 | SEP | 2023 | K. Vanlalawmpuia and Aditya Sankar Medury, “Comparative Analysis of Ferroelectric Quad-FinFET with and without Si3N4 Spacer on Analog/RF, Linearity Performance and Digital Inverter Application with Temperature Variation,” Ferroelectrics, vol. 613, pp. 64-78, September 2023. doi: 10.1080/00150193.2023.2215523 |
| 11 | MAR | 2023 | K. Vanlalawmpuia and Aditya Sankar Medury, “Analysis of Negative Differential Resistance and RF/Analog performance on Drain Engineered Negative Capacitance Dual Stacked-Source Tunnel FET,” IEEE Transactions on Electron Devices, vol. 70, no. 3, pp. 1417–1424, March 2023. doi: 10.1109/TED.2023.3237507 |
| 12 | AUG | 2022 | K. Vanlalawmpuia and Brinda Bhowmick, “Analysis of Temperature Dependent Effects on DC, Analog/RF and Linearity Parameters for a Delta Doped Heterojunction Vertical Tunnel FET,” Silicon, vol. 14, pp. 7517–7529, August 2022. doi: 10.1007/s12633-021-01504-7 |
| 13 | MAY | 2022 | K. Vanlalawmpuia, Suman Kumar Mitra and Brinda Bhowmick, “An Analytical Drain Current Model of Germanium Source Vertical Tunnel Field Effect Transistor,” Nano and Microstructures, vol. 165, no. 207197, May 2022. doi: https://doi.org/10.1016/j.micrna.2022.207197 |
| 14 | APR | 2022 | K. Vanlalawmpuia and Brinda Bhowmick, “Interfacial Charge Analysis and Temperature Sensitivity of Germanium Source Vertical Tunnel FET with Delta-Doped Layer,” Microelectronics Reliability, vol. 131, no. 114512, April 2022. doi: https://doi.org/10.1016/j.microrel.2022.114512 |
| 15 | JAN | 2022 | K. Vanlalawmpuia and Brinda Bhowmick, “Analysis of Hetero-stacked Source TFET and Heterostructure Vertical TFET as Dielectrically Modulated Label-Free Biosensors,” IEEE Sensors Journal, vol. 22, no. 1, pp. 939–947, January 2022. doi: 10.1109/JSEN.2021.3128473 |
| 16 | MAR | 2021 | K. Vanlalawmpuia and Brinda Bhowmick, “Study on induced work‑function variation of titanium metal gate on various electrical parameters for delta‑doped layer germanium source vertical tunnel FET,” Journal of Computational Electronics, vol. 20, pp. 1137-1146, March 2021. doi: https://doi.org/10.1007/s10825-021-01686-8 |
| 17 | OCT | 2020 | K. Vanlalawmpuia, Rajesh Saha and Brinda Bhowmick, “Study of effect of oxide thickness variation on electrical parameters and high frequency characteristics induced by work-function variation for delta-doped germanium-source vertical TFET,” Semiconductor Science and Technology, vol. 35, no. 10, pp. 1-9, October 2020. doi: https://doi.org/10.1088/1361-6641/aba823 |
| 18 | SEP | 2020 | K. Vanlalawmpuia and Brinda Bhowmick, “Investigation of interface trap charges and temperature variation in heterostacked-TFET,” Indian Journal of Physics, vol. 95, no. 9, pp. 1697-1708, September 2020. doi: https://doi.org/10.1007/s12648-020-01834-z |
| 19 | FEB | 2020 | K. Vanlalawmpuia and Brinda Bhowmick, “Optimization of a Hetero-Structure Vertical Tunnel FET for Enhanced Electrical Performance and Effects of Temperature Variation on RF/Linearity Parameters,” Silicon, vol. 13, pp. 155-166, February 2020. doi: https://doi.org/10.1007/s12633-020-00411-7 |
| 20 | OCT | 2019 | K. Vanlalawmpuia and Brinda Bhowmick, “Investigation of a Ge-Source Vertical TFET With Delta-Doped Layer,” IEEE Transactions on Electron Devices, vol. 66, no. 10, pp. 4439-4445, October 2019. doi: 10.1109/TED.2019.2933313 |
| 21 | MAY | 2019 | K. Vanlalawmpuia and Brinda Bhowmick, “Linearity Performance Analysis Due to Lateral Straggle Variation in Hetero-Stacked TFET,” Silicon, vol. 12, pp. 955-961, May 2019. doi: https://doi.org/10.1007/s12633-019-00189-3 |
| 22 | MAR | 2019 | Rajesh Saha, K. Vanlalawmpuia, Brinda Bhowmick and Srimanta Baishya, “Deep insight into DC, RF/analog, and digital inverter performance due to variation in straggle parameter for gate modulated TFET,” Materials Science in Semiconductor Processing, vol. 91, pp 102-107, March 2019. doi: https://doi.org/10.1016/j.mssp.2018.11.011 |
| 23 | MAR | 2019 | K. Vanlalawmpuia, Brinda Bhowmick and Madhuchhanda Choudhury, “Optimisation of fully depleted SiGe channel with raised source/drain buried oxide nMOSFET,” International Journal of Nanoparticles, vol. 11, no. 2, pp. 80-93, March 2019. ISSN: 1753-2507, eISSN: 1753-2515. doi: 10.1504/IJNP.2019.10020324 |
| 24 | SEP | 2018 | K. Vanlalawmpuia, Rajesh Saha and Brinda Bhowmick, “Performance evaluation of hetero-stacked TFET for variation in lateral straggle and its application as digital inverter,” Applied Physics A: Materials Science and Processing, vol. 124, no. 701, pp. 1-8, September 2018. doi: https://doi.org/10.1007/s00339-018-2121-4 |
| International/National Conference Proceedings | |||
|---|---|---|---|
| S.No. | Month | Year | Publication Information |
| 1 | DEC | 2024 | Lalfakzuala, Lalhruaizela Chhangte, C. Lalengmawia and K. Vanlalawmpuia, “Smart-Wi-Cache: A Deep Learning Framework for Online Content Caching at the Wireless Edge,” 17th International Conference on Communication Systems & Networks – Workshop on Machine Intelligence in Networked Data and Systems (MINDS) |
| 2 | MAR | 2017 | K. Vanlalawmpuia, Brinda Bhowmick and Madhuchhanda Choudhury, “Optimization of Electrical Parameters in SiGe Channel nMOSFET,” 2nd IEEE International Conference on DevIC-2017, Kalyani Government Engineering College, March 2017. doi: 10.1109/DEVIC.2017.8073942 |
| Patents | |||
|---|---|---|---|
| S.No. | Month | Year | Publication Information |
| 1 | MAR | 2024 | An Optimized Hetero-structure Vertical Tunnel Based FET Device for Enhanced Electrical Performance (German Patent, No. 202024100509) |
| Book Chapters | |||
|---|---|---|---|
| S.No. | Month | Year | Publication Information |
| 1 | APR | 2022 | K. Vanlalawmpuia and Brinda Bhowmick, “Lateral Straggle Parameter and its impact on Hetero-stacked source Tunnel FET,” Contemporary Trends in Semiconductor Devices, Lecture Notes in Electrical Engineering, vol 850. Springer, Singapore, 2022. ISBN: 978-981-16-9124-9. doi: https://doi.org/10.1007/978-981-16-9124-9_8 |
| 2 | OCT | 2021 | K. Vanlalawmpuia and Brinda Bhowmick, “A Novel Vertical Tunnel FET and Its Applica-tion in Mixed Mode” Nanoelectronic Devices for Security, CRC press, Taylor and Francis group, October 2021. ISBN: 9781003126645. doi: https://doi.org/10.1201/9781003126645 |
Courses Taught
UG:
PG:
Awards / Recognitions
Additional Assignments
| Administrative | ||||
|---|---|---|---|---|
| S.No. | Assignments/Responsibilities | From | To | Organisation |
| 1 | Nodal Officer, Social Media | 26/09/2023 | 26/09/2025 | National Institute of Technology Mizoram |
B.Tech Projects & M.Tech Dissertation
Research Scholars/Ph.D. Supervised
Post-Doctoral Fellows
Academic Responsibility
- Member of Incubation Center : 20/05/2024 - 20/05/2026 @ National Institute of Technology Mizoram
- Faculty Training and Placement Committee : 06/12/2023 - 07/12/2026 @ National Institute of Technology Mizoram
- B.Tech Course Coordinator : 08/08/2023 - 08/08/2025 @ Dept. of ECE, NIT Mizoram, Aizawl, Mizoram, India
Sponsored Research Project
| Title | Detail |
|---|---|
| A Platform for Cost-Efficient Public Health Service Delivery in Mizoram | Designation: Principal Investigator Duration: 2 years (12/12/2023 to 31/12/2025) Status: Ongoing Amount: 37 Lakhs Funding Agency: Technology Innovation Hub (TIH) at IIT Bhilai |
Memberships
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Invited Reviewer
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Training / Conference Attended
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Training / Conference Conducted
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